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Stacked Die (SD) packages which typically consist of bare die stacked and interconnected using wire bond and flip chip connections in one standard package. Configurations include FBGA-SD, FLGA-SD, PBGA-SD, QFP-SD and TSOP-SD.

Package-on-Package (PoP) packages which typically consist of stacking fully tested memory and logic packages eliminating known good die (KGD) issues and providing flexibility in mixing and matching IC technologies. Flip chip PoP options include Bare Die PoP, Molded Laser PoPand an exposed die Molded Laser PoP configuration (PoP-MLP-ED).

Package-in-Package (PiP) packages which typically stack packaged chips and bare chips into one JEDEC standard FBGA. A pre-tested Internal Stacking Module (ISM) Land Grid Array (LGA) and a BGA or a Known/Probed Good Die (KGD) are stacked and interconnected with wire bonding, then molded into a CSP that is indistinguishable from a conventional FBGA package.

embedded Wafer Level BGA (eWLB) - a versatile Fan-Out embedded Wafer Level BGA platform. eWLB's flexible reconstitution manufacturing process can reduce substrate complexity and costs while achieving high performance, smaller package sizes with very dense interconnection in a range of reliable, low-warpage 2D, 2.5D and 3D solutions. JCET's 3D eWLB-SiP and eWLB-PoP solutions include embedded multiple passives and active components, face-to-back or face-to face options, and single-sided, 1.5-sided and double-sided ultra-thin PoP configurations. For applications requiring full 3D integration, JCET's face-to-face (marsupial) eWLB PoP configuration provides a direct vertical interconnection between an application processor die and a memory die through the eWLB mold layer to enable a high bandwidth, very fine pitch structure with performance that parallels TSV technology.

encapsulated WLCSP (eWLCSP™) - an innovative FIWLP package which employs the Fan-out process, also known as the FlexLine™ method, to create this innovative and robust encapsulated WLCSP package.

WLCSP - standard Wafer Level CSP packages. The development of process technologies such as low cure temperature polymers and the use of copper for under bump metallization (UBM) and RDL are enabling higher densities and increased WLCSP package reliability.

2.5D / Extended eWLB - JCET's eWLB-based interposers enable very dense interconnection with more effective heat dissipation and improved processing speed in a proven, low-warpage packaging structure. A 3D eWLB interconnection (including Si partitioning) is accomplished by means of a unique face-to-face bonding approach which eliminates the need for more expensive TSV interconnections while achieving a high bandwidth 3D integration. The simplified materials supply chain and lower overall cost available with an eWLB-based interposer provide a strong technology platform and path for customers to transition their devices to more advanced 2.5D and 3D packages.

2.5D with MEOL integration - One of the first OSATs with established MEOL TSV integration experience in 2.5D packaging, JCET has played an important role in this emerging interconnect technology, and has focused on developing cost effective high volume manufacturing capabilities that make TSV a commercially viable solution. JCET has also been involved in a number of collaborative efforts with customers, institutes, and leading foundries to develop an effective business model for integrated 3D packaging solutions.